1. Field of the Invention
This invention relates to circuit elements formed on the surface of a semiconductor substrate. More particularly this invention relates to capacitors formed on the surface of a semiconductor substrate.
2. Description of Related Art
The art for fabricating a capacitor within an integrated circuit is well known. A capacitor is formed when two conductive materials are separated by an insulator. The capacitance of such a structure is determined by the formula: ##EQU1##
where:
A is the area of one of the conductive materials, PA1 .epsilon. is the permitivity of the insulator, PA1 d is the thickness of the insulator.
FIGS. 1 a, 1b, 1c and 1d illustrate the structure of a metal to metal and a metal to a highly doped polycrystalline silicon capacitor. For a metal to metal capacitor, as shown in FIGS. 1a and 1b, a layer 25 of an insulating material such as silicon dioxide is formed (grown or deposited) on the surface of the semiconductor substrate 30. A layer of the first level metal 5 is placed on the insulating layer 25. A second insulating layer 20 is then formed on the surface of the first level metal 5. The thickness d of the second insulating layer 20 is typically from 460 nanometers to 690 nanometers. The insulating layer 20 is generally silicon dioxide, which has a permitivity of from approximately 3.54.times.10.sup.-11 F/m to 4.43.times.10.sup.-11 F/m. If the insulating layer is 1 .mu.m thick (d) then the capacitance C 15 per unit area is from approximately 0.035 fF/.mu.m.sup.2 to approximately 0.043 fF/.mu.m.sup.2. The total capacitance C15 of the capacitor as shown is the area (l*w) of either the first level metal 5 or the second level metal 10 (whichever is less) multiplied by the capacitance C15.
Other materials such as silicon nitride (Si.sub.x N.sub.y), silicon oxynitride (Si.sub.x O.sub.y N.sub.z), polyimide, or other insulating films may be substituted for the silicon dioxide described above.
Each capacitor formed as shown has a parasitic capacitor Cp 35. The parasitic capacitor Cp 35 is formed by the first level metal 5 and the semiconductor substrate 30. The dielectric of the parasitic capacitor Cp 35 is the first insulating layer 25. The parasitic capacitor Cp 35 typically has a capacitance of from approximately 0.08 fF/.mu.m.sup.2 to approximately 0.12 fF/.mu.m.sup.2.
FIGS. 1c and 1d show a capacitor C 50 having a heavily doped polycrystalline silicon layer 40 as the first plate and the first level metal 5 as the second plate. The capacitor is formed by growing or depositing an insulating material such as silicon dioxide to create the first insulating layer 60 on the surface of the semiconductor substrate 30. The heavily doped polycrystalline silicon layer 40 is deposited on the top of the first insulating layer.
The dielectric of the capacitor C 50 is formed by depositing a second insulating material, again silicon dioxide, on the heavily doped polycrystalline silicon layer 40. The second plate 5 is formed by depositing the first level metal on the surface of the second insulating layer 55. A via 70 is constructed to connect a second level metal layer 45 to the highly doped polycrystalline silicon layer 40.
As described above, a parasitic capacitor 65 is formed between the heavily doped polycrystalline silicon layer 40 and the substrate 30. The capacitance of the parasitic capacitor 65 typically is from 0.08 fF/.mu.m.sup.2 to 0.12 fF/.mu.m.sup.2.
The process of fabrication of the capacitors as shown in FIGS. 1a, 1b, 1c and 1d can be combined to form a stacked capacitor as shown in FIG. 1e. The first insulating layer 60 is formed on the semiconductor substrate 30. The heavily doped polycrystalline silicon layer 40 is formed as above described. The second insulating layer 55 is then formed, as described, on the heavily doped polycrystalline silicon layer 40. Multiple metal layers 5, 45 and 90 are formed having multiple insulating layers 20 and 95 between each of them. The via 70 connects the heavily doped polycrystalline silicon layer 40 to the second level metal layer 45. The via 92 connects the first level metal layer 5 to the third level metal layer 90. This creates a structure where the multiple metal layers 5, 45, and 90 and the highly doped polycrystalline silicon layer 40 are interleaved to form the stacked capacitor. The capacitor C1 75 is formed by the highly doped polycrystalline silicon layer 40 and the first level metal layer 5. The capacitor C2 80 is formed by the first and second level metal layers 5 and 45. The capacitor C3 85 is formed by the second and third level metal layers 45 and 90. The total capacitance of the stacked capacitor is the sum of the capacitors C1, C2, and C3.
As described in FIGS. 1c and 1d, the parasitic capacitor Cp 65 is formed between the heavily doped polycrystalline silicon layer 40 and the semiconductor substrate 30.
Typically, in an integrated circuit design, the layer 40 that forms the parasitic capacitor Cp 65 is connected in a way so as to minimize the effect of the parasitic capacitor Cp 65. One example of this is connecting the layer 40 to the ground reference point such that both terminals of the parasitic capacitor Cp 65 are at an equal potential. Often the layer 40 that forms the parasitic capacitor Cp 65 with the semiconductor substrate 30 is termed the bottom plate of the capacitor and conversely the layers 5 and 90 not attached to the parasitic capacitor Cp 65 are connected to the more noise sensitive nodes of an integrated circuit and are termed the top plate of the capacitor. In some applications of the capacitor, it can not be connected as above described. In such cases one will have to take the effect of the parasitic capacitor Cp 65 in account. The lower the value of the parasitic capacitor Cp 65, when compared to the capacitance per unit area Co, the less impact the parasitic capacitor Cp 65 has on the design of the stacked capacitor.
Table 1. shows the designation of the top plate, bottom plate, the capacitance per unit area Co of the structure, and the parasitic capacitance factor Kp.
TABLE 1 ______________________________________ Type Top Plate Bottom Plate ##STR1## ______________________________________ Metal 1/ Metal 2 Metal 1 0.04 fF/.mu.m.sup.2 0.4 Metal 2 (FIG. 1a/1b) Metal 1/Poly Metal 1 Poly 0.06 fF/.mu.m.sup.2 0.6 (FIG. 1c/1d) Stacked Metal 1/Metal 3 Metal 2/Poly 0.14 fF/.mu.m.sup.2 1.4 Metal 1/ Metal 2/ Metal 3/Poly (FIG. 1e) ______________________________________
FIG. 2 illustrates a second method of fabricating a capacitor on a p-type semiconductor substrate 200. An n-type material is diffused to a lightly doped concentration into the p-type semiconductor substrate 200 to form the well 205. Heavily doped n-type material is further diffused into the p-type semiconductor substrate 200 within the well 205 to form the contact areas 210. The contact metalization 225 forms the connection between the well 205 and the first level metal layer 230. A thin insulating layer 215 is formed on the surface of the p-type semiconductor substrate 200 above the well 205. A heavily doped polycrystalline silicon layer 220 is formed on the thin insulating layer 215. The top plate capacitor C 235 is formed by the heavily doped polycrystalline silicon layer 220. The bottom plate of the capacitor C 235 is formed by the well 205 with the thin insulating layer 215 forming the dielectric of the capacitor C 235. The capacitance per unit area Co of the capacitor C 235 has a very high value that is approximately 4.8 fF/.mu.m.sup.2 for a typical 0.35 .mu.m, because of the dielectric of the very thin insulating layer 215, between the plates 215 and 205. The capacitance per unit area Co of the capacitor C 235 has a range of from 4.3 fF/.mu.m-5.3 fF/.mu.m.sup.2 for the 0.35 .mu.m process.
A parasitic capacitor Cp 240 is the junction capacitance between the well 205 and the substrate 200, which is typically 0.24 fF/.mu.m.sup.2. In the capacitor structure, as shown, the parasitic capacitance factor Kp is 20.0, this is considered a very good value.
As a voltage is placed across a capacitor, the shifting of the charges from one plate to the other can deplete the available charges from the plate having the most negative voltage. This depletion of the charges makes the capacitance value a function Kv of the voltage applied across the capacitor. Metal layers and highly doped polycrystalline silicon layers have sufficient charges available in their structure that the voltage at which depletion becomes a factor is much larger than the breakdown voltage of the dielectric between the layers. Usually the n-well 205 is lightly doped because of other constraints. Unfortunately, the lightly doped n-well 205 becomes depleted of charges at a much lower voltage than the voltage level of the power supply voltage source, because of the very thin dielectric. This results in a very large voltage function Kv.
U.S. Pat. No. 5,108,941 (Paterson et al.) describes a method for forming a metal to polycrystalline silicon capacitor on a field oxide layer on a semiconductor substrate surface. After the formation of the patterned polycrystalline silicon layer, a multi-level dielectric is formed, and a via is etched there through to a polycrystalline silicon lower electrode. The capacitor dielectric such as an oxide/nitride layered dielectric is then deposited. Contacts are etched to a diffusion layer and to polycrystalline silicon electrodes as desired, and metal is deposited and patterned to form the top electrode of the capacitor over the capacitor dielectric, and to make contact as desired to diffusion and to polycrystalline silicon.
U.S. Pat. No. 4,914,497 (Kondo) discloses a semiconductor device with a metal-insulator semiconductor (MIS) capacitor. The MIS capacitor uses an oxidation-resist film for forming a field oxide film partly buried in a semiconductor substrate. The oxidation-resist film is created by means of the selective oxidation technique and is employed as a dielectric. A peripheral edge portion of the oxidation-resist film is turned up at a bird's-beak-shaped edge portion of the field oxide film, so that a gap space is produced between the peripheral edge portion of the oxidation-resist film and the bird's-beak-shaped edge portion of the field oxide film. An insulator layer is formed at the peripheral edge portion of the oxidation-resist film. An elongated upper conductor layer of the MIS capacitor is formed on the oxidation-resist film to form the top plate of the MIS capacitor.
U.S. Pat. No. 5,130,267 (Kaya et al.) teaches split metal plate capacitor with a polycrystalline silicon electrode as a bottom plate and a split metal layer as a top plate. Subsequent to the formation of a patterned polycrystalline silicon layer preferably silicide clad, the capacitor dielectric is deposited on the polycrystalline silicon layer. A first metal layer formed of a refractory metal (such as Mo, W, or Ti), alloy (titanium-tungsten) or compound (titanium nitride) is deposited over the capacitor dielectric. The first metal layer is patterned and etched to define the size of the metal the size of the polycrystalline silicon/silicide capacitor. Multilevel dielectric, such as phososilicate glass (PSG) or borophososilicate glass, is deposited over the first metal layer. A contact via is etched through the multilevel dielectric to the first metal layer. Contacts are etched at this same time to diffusion and to polycrystalline silicon electrodes as desired. A second metal layer is then deposited and patterned to contact the top plate of the capacitor over the capacitor dielectric, and to make contact as desired to the diffusion and to the polycrystalline silicon.
U.S. Pat. No. 4,377,029 (Ozawa) describes a process for fabricating a bipolar integrated circuit in which the insulation layer separating the diffusion layer connected to a lower part electrode of a capacitor from the upper electrode may be made thinner without causing short circuiting between the upper electrode and the lower electrode. Thus, the capacitance of the capacitor region may be increased and the packaging density of the integrated circuit may be improved.